The First Clock Cycle Is A Real BIST

The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that the user can be assured that their system function is downloaded to a fault-free device. In this paper, we present case studies of developing BIST configurations for some of the less thought of, though equally important, logic resources in current FPGAs including programmable clock buffers and cyclic redundancy code (CRC) modules. While seemingly trivial, these modules present interesting testing challenges in FPGAs. Among the most interesting challenges are the problems, and importance, associated with the very first clock cycle of the BIST sequence when testing FPGA initialization capabilities, or lack thereof, via the configuration download. While the conditions may last for only one clock cycle, testing these features is essential to insure the intended system function is properly initialized during operation. 1